Solid state imaging device and differential circuit having an expanded dynamic range

ABSTRACT

A solid-state imaging device that is configurable into a small size appropriate for expanding dynamic range includes: a photodiode which is a photoelectric conversion unit that generates charge by incident light; a MOS transistor which is connected to the photodiode and transfers the charge; a floating diffusion region which is a first accumulation unit which accumulates the charge via the MOS transistor; a MOS transistor which is a second transfer unit connected to the floating diffusion region and connected in series to the MOS transistor; and a MOS transistor which is an output unit which outputs, via the MOS transistor, a signal voltage in accordance with an amount of the charge.

TECHNICAL FIELD

The present invention relates to a solid-state imaging device used in adigital camera, and relates particularly to a technique of expandingdynamic range of the solid-state imaging device.

BACKGROUND ART

Conventionally, a complementary MOS (CMOS) solid-state imaging devicewhich is already in practical use reads charge that is accumulated in aphotodiode included in each pixel through an amplifying circuitincluding a metal oxide semiconductor (MOS) transistor.

The CMOS solid-state imaging device can be driven with low voltage andlow power consumption, and is particularly used as an image input devicefor a cellular phone. Furthermore, in recent years, the CMOS solid-stateimaging device has been incorporated in a monitoring camera and anin-vehicle camera.

A general dynamic range (a ratio between maximum intensity and minimumintensity of incident light to which an output is responsive) of theCMOS solid-state imaging device is approximately 60 dB to 80 dB, and itis expected to expand the dynamic range to approximately 100 dB to 120dB which is comparable to a naked human eye or silver salt film.Particularly, it is further expected to expand the dynamic range whenusing the CMOS solid-state imaging device in the in-vehicle camera, themonitoring camera, or the like which requires capturing a recognizableimage of an entire object having brightness significantly different fromportion to portion.

To meet this demand, there are some known techniques of expanding thedynamic range by accumulating, in a large-volume capacitor, the chargegenerated in a light-receiving element (for example, see PatentLiterature 1 and Patent Literature 2).

FIG. 1 is a circuit diagram showing a pixel circuit of a solid-stateimaging device disclosed in Patent Literature 1.

The pixel circuit shown in FIG. 1 includes: a photodiode PD; a parasiticcapacitor of a photodiode PD, or a capacitor C1 that is intentionallyformed; a reset transistor M1; a transfer switch M2; a selection switchM4; a source follower transistor M6; a capacitor C2 which is agate-source capacitor of the source follower transistor M6; a transferswitch M3; a selection switch M5; a source follower transistor M7; and acapacitor C3 which is a gate-source capacitor of the source followertransistor M7.

This configuration allows the charge accumulated in the photodiode PDand the capacitor C1 to be output via two paths: a first path via thesource follower transistor M6 and a second path via the source followertransistor M7.

The pixel circuit shown in FIG. 1 can expand the dynamic range asfollows.

First, the charge accumulated in the photodiode PD and the capacitor C1is discharged to a supply of reset voltage VR via the reset transistorM1.

During a charge accumulation period, the charge generated by incidentlight on the photodiode PD is accumulated in the photodiode PD and thecapacitor C1.

When turning on the transfer switch M2 and the transfer switch M3, thevoltage of each of the capacitor C2 and the capacitor C3 variesaccording to the amount of charge accumulated in the photodiode PD andthe capacitor C1.

Assuming, as an example, a gate size of the source follower transistorM6 as W=1 μm, L=1 μm, and a gate size of the source follower transistorM7 as W=10 μm, L=10 μm, the gate-source capacitance of the sourcefollower transistor M7 is ten times larger than the gate-sourcecapacitance of the source follower transistor M6. Accordingly, thecapacitance of the capacitor C3 is ten times larger than the capacitanceof the capacitor C2.

Accordingly, turning on the transfer switch M3 expands the dynamic rangeby ten times compared to the case of turning on the transfer switch M2.

FIG. 2 is a circuit diagram showing a pixel circuit of a solid-stateimaging device disclosed in Patent Literature 2.

The pixel circuit shown in FIG. 2 includes: a photoelectric conversionunit (hereinafter, described as a PD unit) 371; a transfer transistor372 which is provided adjacent to the PD unit 371 and transfersphotocharge; a diffusion region (hereinafter described as an FD region)373 provided in connection with the PD unit 371 via the transfertransistor 372); a first capacitor 374 and a second capacitor 375 whichaccumulate a charge overflowing from the PD unit 371 during a chargeaccumulating operation; a reset transistor 376 which is provided inconnection with the first capacitor 374 and discharges the signal chargefrom the first capacitor 374, the second capacitor 375, and the FDregion 373; a first accumulation transistor 377 provided between the FDregion 373 and the first capacitor 374; a second accumulation transistor378 provided between the first capacitor 374 and the second capacitor375; an amplifying transistor 379 which reads, as voltage fluctuation,the signal charge accumulated in the FD region 373, or the signal chargeaccumulated in the FD region 373 and the first capacitor 374, or thesignal charge accumulated in the FD region 373, the first capacitor 374,and the second capacitor 375; and a selection transistor 380 which isprovided in connection with the amplifying transistor 379 and selectsthe pixel or a pixel block including the pixel.

The pixel circuit shown in FIG. 2 can expand dynamic range as follows.

First, prior to charge accumulation, the first accumulation transistor377 and the second accumulation transistor 378 are turned on, and thetransfer transistor 372 and the reset transistor 376 are turned off.Subsequently, with the reset transistor 376 and the transfer transistor372 held in an On-state, the FD region 373 and the first and secondcapacitors 374 and 375 are reset.

Subsequently, a first noise charge N1, which is introduced into the FDregion 373, the first capacitor 374, and the second capacitor 375 afterturning off the reset transistor 376, is read out. In the reading, thefirst noise charge N1 includes a fixed pattern noise component derivedfrom a threshold voltage of the amplifying transistor 379.

Subsequently, with the second accumulation transistor 378 held in anOff-state, the signal charge accumulated in the FD region 373, the firstcapacitor 374, and the second capacitor 375 is distributed according toa capacitance ratio between the FD region 373, the first capacitor 374,and the second capacitor 375.

Of the distributed charges, a second noise charge N2, which isdistributed to the FD region 373 and the first capacitor 374, is readout. In the reading, the second noise charge N2 also includes afixed-pattern noise component derived from the threshold voltage of theamplifying transistor 379.

Subsequently, during the charge accumulation period, with the firstaccumulation transistor 377 held in the On-state and the secondaccumulation transistor 378, the reset transistor 376, and the selectiontransistor 380 held in the Off-state, the charge is accumulated in thePD unit 371, and an excess amount of the generated charge which exceedsa maximum charge accumulation amount of the PD unit 371 is added to thenoise charge N2 and accumulated in the FD region 373 and the firstcapacitor 374, via the transfer transistor 372 and the firstaccumulation transistor 377.

Furthermore, the charge exceeding the maximum charge accumulation amountof the PD unit 371 and the first capacitor 374 is accumulated in thesecond capacitor 375 via the second accumulation transistor 378.

This operation allows the charge overflowing from the PD unit 371 to beaccumulated in another capacitor, so that the dynamic range is expanded.

Subsequently, after completion of the charge accumulation period, withthe selection transistor 380 held in the On-state and the firstaccumulation transistor 377 held in the Off-state, the chargeaccumulated in the FD region 373 and the first capacitor 374 isdistributed according to the capacitance ratio between the FD region 373and the first capacitor 374.

Subsequently, a signal charge N3 distributed to the FD region 373 isread out. In the reading, the signal charge N3 also includes a fixedpattern noise component derived from the threshold voltage of theamplifying transistor 379.

Subsequently, with the transfer transistor 372 held in the On-state, thecharge accumulated in the PD unit 371 is transferred to the FD region373, and a signal charge S1 in the FD region 373 is added to the signalcharge N3, to be read out.

Subsequently, with the first accumulation transistor 377 held in theOn-state, the signal charge S1 in the FD region 373 and the signalcharge S2 in the first capacitor 374 are mixed to be read out.Subsequently, with the second accumulation transistor 378 held in theOn-state, the signal charge S1 in the FD region 373, the signal chargeS2 in the first capacitor 374, and the signal charge S3 in the secondcapacitor 375 are mixed to be read out.

Subsequently, with the reset transistor 376 held in the Off-state, theFD region 373, the first capacitor 374, and the second capacitor 375 arereset.

A solid-state imaging device as disclosed in Patent Literature 2 expandsdynamic range using a pixel circuit which keeps a high aperture ratio,by detecting the signal charge from each pixel by repeating theoperation described above.

CITATION LIST Patent Literature

[PTL 1] Japanese Unexamined Patent Application Publication No.2003-134396

[PTL 2] Japanese Unexamined Patent Application Publication No.2006-245522

SUMMARY OF INVENTION Technical Problem

However, Patent Literature 1 discloses a technique of expanding dynamicrange by increasing the gate-source capacitances of the source followertransistors M6 and M7. Thus, to increase the dynamic range, it isnecessary to increase gate size, which causes, as a result, a problem ofincrease in chip size in the solid-state imaging device.

In addition, the technique disclosed in Patent Literature 2 has thefollowing problem.

During the charge accumulation period of the PD unit 371, apredetermined voltage is applied to the FD region 373. In addition, then-type impurity concentration of the configuration of the FD region 373is higher than that of the PD unit 371, and a contact is formed toconnect a gate electrode of the amplifying transistor 379 and adiffusion layer of the FD region 373. Thus, during the chargeaccumulation period, leakage current causes a decline in hold voltage ofthe FD region 373, which makes it difficult to perform a completetransfer of the accumulated charge from the PD unit 371 to the FD region373, and causes, as a result, a problem of occurrence of afterimage.

In addition, a predetermined voltage is also applied to the FD region373, the first capacitor 374, and the second capacitor 375 whichaccumulate the charge leaking from the PD unit 371, and the FD region373 includes a diffusion layer including a high-concentration n-typeimpurity, and is connected to a contact including a metal material. Withthis, an inflow of charge caused by leakage current reduces thecapacitances of the FD region 373, the first capacitor 374, and thesecond capacitor 375 for accumulating the charge from the PD unit 371.This results in a problem of insufficient expansion of dynamic range.

In addition, due to the configuration in which a charge leakage from thePD unit 371 is accumulated in the FD region 373, the first capacitor374, and the second capacitor 375, the dynamic range is determined bythe capacitances of such capacitors, that is, the amount of charge thatcan be accumulated by these capacitors. This causes another problem ofinsufficient expansion of dynamic range.

In addition, since one pixel needs to include three capacitors, that is,the FD region 373, the first capacitor 374, and the second capacitor375, it is difficult to secure a sufficient aperture area that is anarea of the PD unit 371, and this causes a problem of reducedsensitivity. In addition, since it is difficult to downsize the pixel,there is also a problem of difficulty in downsizing the chip size andforming a high-resolution imaging device.

The present invention is conceived to solve these problems, and it is anobject of the present invention to provide a solid-state imaging devicethat is suited for expanding dynamic range and is configurable into asmall size.

Solution to Problem

To achieve the above object, a solid-state imaging device according toan aspect of the present invention is a solid-state imaging deviceincluding a plurality of pixel circuits two-dimensionally arranged on asemiconductor substrate, and the solid-state imaging device includes: aphotoelectric conversion unit which generates a charge from incidentlight; a first transfer unit which is connected to the photoelectricconversion unit and transfers the charge; a first accumulation unitwhich accumulates the charge via the first transfer unit; a secondtransfer unit connected to the first accumulation unit and connected inseries to the first transfer unit; and an output unit which outputs asignal voltage that is a voltage according to an amount of the chargevia the second transfer unit.

In addition, each of the first and second transfer units may include aMOS transistor, and a drain of the first transfer unit may be connectedto a source of the second transfer unit.

In addition, the solid-state imaging device may further include a secondreset unit which sets a voltage of a connection point between the secondtransfer unit and the output unit to a reset voltage, and the outputunit may further output a reference voltage in a state where the resetvoltage is applied to the connection point.

In addition, the photoelectric conversion unit, the transfer unit, thefirst accumulation unit, the second transfer unit, the output unit, andthe second reset unit may be provided in each of the plurality of pixelcircuits.

This allows continuously transferring the charge accumulated in thephotoelectric conversion unit during different lengths of accumulationtime, and allows outputting, via the second transfer unit, a result ofthe addition performed in the first accumulation unit, thus making itpossible to realize expanding dynamic range by adding optical signalcharges within the pixel circuit, without requiring a circuit for addingsignals to be provided outside the solid-state imaging device.

In addition, preferably, the second transfer unit includes a MOStransistor, and the first accumulation unit has no contact with a metalmaterial.

This makes it possible to decrease leakage current in the firstaccumulation unit.

In addition, the first transfer unit in each of the plurality of pixelcircuits may transfer the charge generated in the photoelectricconversion unit to the first accumulation unit, the charge beinggenerated from the incident light entering during a time period commonlydetermined for each of the plurality of pixel circuits.

This allows a global shutter operation.

In addition, the first transfer unit in each of the plurality of pixelcircuits may transfer a plurality of charges generated in thephotoelectric conversion unit to the first accumulation unit, theplurality of charges each being generated from the incident lightentering during a corresponding one of a plurality of time periodscommonly determined for each of the plurality of pixel circuits andhaving lengths different from each other, and the first accumulationunit may add and accumulate all the plurality of charges that aretransferred.

This makes it possible to obtain an image signal having wide dynamicrange.

In addition, the solid-state imaging device may further include: adifferential circuit which detects a difference between the signalvoltage and the reference voltage, and the differential circuit mayinclude: a first capacitor and a second capacitor that are connected inseries; and an initializing switch through which an initializing voltagethat is predetermined is applied to a connection point between the firstand second capacitors, and in a state where the initializing voltage isapplied to the connection point, the differential circuit may hold adifference voltage in the first capacitor and the initializing voltagein the second capacitor, and may subsequently divide the referencevoltage between the first and second capacitors, the difference voltagebeing a difference between the signal voltage and the initializingvoltage.

In addition, preferably, the second capacitor includes a plurality ofseparate capacitors one of which can be selectively connected in seriesto the first capacitor, and all of which can be coupled in parallel, andthe differential circuit may divide the reference voltage between thefirst capacitor and each of the plurality of separate capacitors andsubsequently couple all of the plurality of separate capacitors inparallel.

This makes it possible to obtain a video signal of high output levelwith less noise.

In addition, the solid-state imaging device may further include: asecond accumulation unit which is connected to a connection pointbetween the second transfer unit and the output unit and accumulates thecharge via the second transfer unit; a first reset unit which dischargesthe charge accumulated in the first accumulation unit; and

a second reset unit which discharges the charge accumulated in thesecond accumulation unit, and the output unit may further output areference voltage in a state where the charge accumulated in the secondaccumulation unit is discharged.

In addition, preferably, the first reset unit applies a first voltage tothe first accumulation unit, the second reset unit applies a secondvoltage to the second accumulation unit, and a maximum value of thefirst voltage is equal to or lower than a maximum value of the secondvoltage.

This allows separately adjusting the voltage applied to the firstaccumulation unit and the voltage applied to the second accumulationunit, allows a complete charge transfer from the first accumulation unitto the second accumulation unit, and allows increasing the amount ofaccumulated charge as a result of increase in the applied voltage evenwhen the area of the first accumulation unit is reduced, thus making itpossible to realize a smaller solid-state imaging device that achieveshigh resolution and wide dynamic range.

In addition, preferably, a capacity of the photoelectric conversion unitis smaller than a capacity of the first accumulation unit.

This allows all the charges accumulated in the photoelectric conversionunit to be transferred to the first accumulation unit, thus making itpossible to realize a solid-state imaging device that achieves highresolution and wide dynamic range.

In addition, preferably, a capacity of the first accumulation unit isequal to or smaller than a capacity of the second accumulation unit.

This allows all the charge accumulated in the first accumulation unit tobe transferred to the second accumulation unit, thus making it possibleto realize a solid-state imaging device that achieves high resolutionand wide dynamic range.

In addition, the output unit has an amplifying transistor.

This allows the accumulated charge to be output from the photoelectricconversion unit included in the pixel circuit to the outside of thesolid-state imaging device, thus making it possible to obtain an image.

In addition, the photoelectric conversion unit may include: a firstregion formed near a surface of the semiconductor substrate, the firstregion being of a first conductivity type; and a second regionsurrounding bottom and lateral sides of the first region, the secondregion being of a second conductivity type different from the firstconductivity type, and a third region of the second conductivity typemay be formed in a surface of a portion on which the first region isformed, the portion being included in the semiconductor substrate.

This decreases leakage current in and out of the photoelectricconversion unit and allows, concurrently with suppressing loss due tothe leakage, transferring the charge generated in the photoelectricconversion unit to the first accumulation unit, thus making it possibleto realize a solid-state imaging device that achieves high resolutionand wide dynamic range.

In addition, the first accumulation unit may include: a fourth regionformed near a surface of the semiconductor substrate, the fourth regionbeing of a first conductivity type; and a fifth region surroundingbottom and lateral sides of the fourth region, the fifth region being ofa second conductivity type different from the first conductivity type,and a sixth region of the second conductivity type may be formed in asurface of a portion on which the fourth region is formed, the portionbeing included in the semiconductor substrate.

This decreases leakage current in and out of the first accumulation unitand allows, concurrently with suppressing loss due to the leakage,transferring the charge generated in the photoelectric conversion unitto the first accumulation unit, thus making it possible to realize asolid-state imaging device that achieves high resolution and widedynamic range.

In addition, the photoelectric conversion unit may include: a firstregion formed near a surface of the semiconductor substrate, the firstregion being of a first conductivity type; and a second regionsurrounding bottom and lateral sides of the first region, the secondregion being of a second conductivity type different from the firstconductivity type, the first accumulation unit may include: a fourthregion formed near the surface of the semiconductor substrate, thefourth region being of the first conductivity type; and a fifth regionsurrounding bottom and lateral sides of the fourth region, the fifthregion being of the second conductivity type different from the firstconductivity type, and an impurity concentration of the first region maybe equal to or lower than an impurity concentration of the fourthregion.

This decreases the leakage current in and out of the first accumulationunit, thus making it possible to realize a solid-state imaging devicethat achieves high resolution and wide dynamic range.

In addition, the present invention can be realized not only as such asolid-state imaging device but also as a differential circuit.

Advantageous Effects of Invention

A solid-state imaging device according to an implementation of thepresent invention includes: a photoelectric conversion unit whichgenerates a charge from incident light; a first transfer unit which isconnected to the photoelectric conversion unit and transfers the charge;a first accumulation unit which accumulates the charge via the firsttransfer unit; a second transfer unit connected to the firstaccumulation unit and connected in series to the first transfer unit,and thus, by continuously transferring to the first accumulation unit,the charges accumulated in the photoelectric conversion unit during aplurality of accumulation periods having different lengths, andoutputting, via the second transfer unit, the result of the additionperformed in the first accumulation unit, it is possible to realize asolid-state imaging device that allows expanding dynamic range, byadding optical signal charges within the pixel circuit, withoutrequiring another circuit for adding the signals to be provided outsidethe solid-state imaging device.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a circuit diagram showing a configuration of a main part of aconventional solid-state imaging device.

FIG. 2 is a circuit diagram showing a configuration of a main part of aconventional solid-state imaging device.

FIG. 3 is a circuit diagram showing a configuration of a main part of asolid-state imaging device according to a first embodiment of thepresent invention.

FIG. 4 is a circuit diagram showing a configuration of a main part ofthe solid-state imaging device according to a variation of the firstembodiment of the present invention.

FIG. 5 is a cross-sectional schematic diagram of a pixel circuitaccording to the first embodiment of the present invention.

FIG. 6 is a timing chart for driving the solid-state imaging deviceaccording to the first embodiment of the present invention.

FIG. 7 is a timing chart for driving the solid-state imaging deviceaccording to the first embodiment of the present invention.

FIG. 8 is a circuit diagram showing a general noise canceling circuit.

FIG. 9 is a circuit diagram showing a pixel circuit of a solid-stateimaging device according to a second embodiment of the presentinvention.

FIG. 10 is a cross-sectional schematic diagram of a pixel circuitaccording to the second embodiment of the present invention.

FIG. 11 is a layout diagram of the pixel circuit according to the secondembodiment of the present invention.

FIG. 12 is a timing chart for driving the solid-state imaging deviceaccording to the second embodiment of the present invention.

DESCRIPTION OF EMBODIMENTS

Hereinafter, embodiments of the present invention will be described withreference to the drawings.

[Embodiment 1]

First, a solid-state imaging device according to a first embodiment ofthe present invention will be described.

FIG. 3 is a circuit diagram showing a configuration of a main part ofthe solid-state imaging device according to the first embodiment.

A solid-state imaging device shown in FIG. 3 includes: a photodiode 101;metal oxide semiconductor (MOS) transistors 102, 104, 105, 106, 107,110, 112, 113, 114, 115, and 116; capacitors 111, 117, 118, 119, and120; a vertical common signal line 108; and a floating diffusion region103.

The photodiode 101 is a light-receiving element which generates anoptical signal charge according to light-receiving intensity andexposure time.

The MOS transistor 102 is an example of the first transfer unit, and isa charge transfer gate through which the signal charge generated in thephotodiode 101 is transferred to the floating diffusion region 103. Whenthe MOS transistor 102 is turned on, the charge generated in thephotodiode 101 is transferred to the floating diffusion region 103. Thisgenerates a voltage according to the amount of the transferred chargeand the capacitance of the floating diffusion region 103.

The MOS transistor 104 is an example of the second transfer unit, and isa switch through which the voltage generated in the floating diffusionregion 103 is transmitted to the gate of the MOS transistor 106.

The MOS transistor 105 is an example of the first reset unit, and is areset transistor which sets the voltage of the gate of the MOStransistor 106 to a voltage VRST.

The MOS transistor 107 is a row selection transistor which transmits, tothe vertical common signal line 108, the voltage obtained from the MOStransistor 106 according to the voltage of the floating diffusion region103.

The MOS transistors 110, 112, 113, 114, 115, and 116, and the capacitors111, 117, 118, 119, and 120 are included in the noise canceling circuit.

Enclosed by a dotted line is a pixel circuit 121 which is provided ineach of a plurality of pixels arranged in an array in the solid-stateimaging device.

FIG. 4 is a circuit diagram showing a variation of the solid-stateimaging device. In the solid-state imaging device according to thisvariation, signals from the respective pixels are transmitted to thevertical common signal line 108, and are subsequently amplified by theamplifier 109 and transmitted to the noise canceling circuit. In otheraspects, the same is applicable as described above.

FIG. 5 is a cross-sectional schematic diagram of a main part of thepixel circuit 121.

As the photodiode 101, an n⁻-type impurity region 152 is provided in asubstrate 151 including a p-type semiconductor, and a p-type impurityregion 153 is provided on the n⁻-type impurity region 152, in a surfaceof the substrate 151. In addition, a lateral and bottom perimeter of then⁻-type impurity region 152 is surrounded by a p-type impurity region.This prevents the charge, which is generated at a point having a factorcausing leakage current, that is, having many defects in the surface ofthe substrate 151, from being accumulated in the photodiode 101, thusincreasing sensitivity.

In addition, as the floating diffusion region 103, an n-type impurityregion 154 is provided in the substrate 151, and a p-type impurityregion 155 is provided on the n-type impurity region 154, in the surfaceof the substrate 151. This prevents the charge, which is generated at apoint having a factor causing leakage current, that is, having manydefects in the surface of the substrate 151, from being accumulated inthe floating diffusion region 103, thus allowing securing a sufficientamount of charge to be accumulated in the floating diffusion region 103as signal charges.

The MOS transistor 102 is formed to include: the n⁻-type impurity region152, the n-type impurity region 154, and a gate electrode 163. Byapplying voltage to the gate electrode 163 of the MOS transistor 102, itis possible to transfer all the charge accumulated in the photodiode 101to the floating diffusion region 103.

The MOS transistor 104 is formed to include: the n-type impurity region154, an n⁺-type impurity region 156, and a gate electrode 168. Byapplying voltage to the gate of the MOS transistor 104, the voltage ofthe floating diffusion region 103 is transmitted to the gate of the MOStransistor 106 via the n⁺-type impurity region 156 and a contact notshown in the figure.

The MOS transistors 106 and 107 apply, to the vertical common signalline 108, a voltage according to the voltage of the floating diffusionregion 103.

The MOS transistor 105 is formed to include: the n⁺-type impurity region156, an n⁺-type impurity region 171, and a gate electrode 170.

In this configuration, the n⁻-type impurity region 152 is formed at aconcentration of 1E13 to 1E16/cm³; the n-type impurity region 154 isformed at a concentration of 1E14 to 1E18/cm³; and the n⁺-type impurityregion 156 is formed at a concentration of 1E15 to 1E20/cm³. Inaddition, the p-type impurity regions 153 and 155 are formed at aconcentration of 1E15 to 1E20/cm³. Note that generally, increasing thelevel of impurity concentration increases leakage current, and thus then-type impurity region 154 as the floating diffusion region 103 shouldpreferably be formed at low concentration.

In addition, the configuration is designed such that the capacitance ofthe floating diffusion region 103 is, for example, three times or morelarger than the capacitance of the photodiode 101, by, for example,increasing the area of the n-type impurity region 154, increasing thelevel of impurity concentration, or increasing the voltage to beapplied. This, for example, makes it possible to transfer, to thefloating diffusion region 103, all the charges of respective amountsaccumulated in the photodiode 101 during three types of accumulationtime having different lengths and to add the transferred charges, thusallowing expanding the dynamic range of the pixel circuit as describedin detail below.

An operation of the solid-state imaging device configured as above willbe described.

FIG. 6 is a timing chart indicating an example of timing for driving thesolid-state imaging device.

RST is a control signal applied to the gate of the MOS transistor 105;READ is a control signal applied to the gate of the MOS transistor 104as a switch; TRAN is a control signal applied to the gate of the MOStransistor 102 as a transferer; SHNC is a control signal applied to thegate of the MOS transistor 110; CLDCNC is a control signal applied tothe gate of the MOS transistor 112; S1, S2, S3, and S4 are controlsignals applied to gates of the MOS transistors 113, 114, 115, and 116,respectively; and SEL is a control signal applied to the gate of the MOStransistor 107.

At time point t1, the charge generated in the photodiode 101 duringaccumulation time T1 by turning on the MOS transistor 102 in thetransferer is transferred to the floating diffusion region 103. Thisoperation is performed almost simultaneously in all pixels.

At time point t4, the control signal RST is applied to the gate of theMOS transistor 105, so as to set, to VRST, a voltage of a partialcircuit A shown in FIG. 3, which includes the gate of the MOS transistor106.

Subsequently, at time point t5, the control signals READ, SEL, SHNC,CLDCNC, S1, S2, S3, and S4 are applied. The MOS transistor 104, to whichthe control signal READ is applied, turns on and transmits the voltageof the floating diffusion region 103 to the gate of the MOS transistor106. A voltage VSIG, which is a result of dividing the chargetransferred from the photodiode 101 at time point t1 by the capacitanceof the floating diffusion region 103, is transmitted to the gate of theMOS transistor 106. In practice, since the partial circuit A includes afloating capacitor, a voltage resulting from voltage division betweenthe floating diffusion region 103 and the floating capacitor istransmitted.

The MOS transistor 107, to which the control signal SEL is applied,turns on and transmits, to the vertical common signal line 108, thevoltage that is output from the MOS transistor 106. The MOS transistor110, to which the control signal SHNC is applied, turns on and transmitsa voltage VSIG1 according to VSIG to an upper electrode (whichrepresents an electrode shown in an upper side in the figure;hereinafter, each electrode is described as an upper electrode or alower electrode, depending on the position at which it is shown in thefigure) of the capacitor 111. In addition, the MOS transistor 112, towhich the control signal CLNCDC is applied, turns on and transmits avoltage VCLDC to a lower electrode of the capacitor 111. At this point,the capacitor 111 is charged, so that the voltage across the capacitor111 becomes (VSIG1−VCLDC). In addition, by turning on the MOStransistors 113, 114, 115, and 116 by applying the control signals S1,S2, S3, and S4, the capacitors 117, 118, 119, and 120 are initialized tothe voltage VCLDC.

At time point t6, the control signal RST is applied to the gate of theMOS transistor 105, and the control signal S1 is applied to the gate ofthe MOS transistor 113, so that the partial circuit A is set to thevoltage VRST. That is, the voltage of the partial circuit A which isVSIG at time point t5 becomes VRST at time point t6.

As a result, the voltage of the upper electrode of the capacitor 111,which is VSIG1 at time point t5, is changed to VRST0 at time point t6according to VRST, so that a voltage (VSIG1−VCLDC−VRST0) is set for thecapacitor 117. In addition, for the sake of conciseness, assuming thatthe capacitance of the capacitor 111 is sufficiently larger than thecapacitance of one of the capacitors 117 to 120, the voltage(VSIG1−VCLDC−VRST0) is set for each of the capacitors 118, 119, and 120at time points t7, t8, and t9 as the time point t6.

At time point t10, the control signals S1, S2, S3, and S4 are applied tothe MOS transistors 113, 114, 115, and 116, respectively, and thecapacitors 117, 118, 119, and 120 are connected in parallel. In FIG. 3,a voltage at point B with reference to VCLDC is(VSIG1−VCLDC−VRST0)+VCLDC, and a voltage (VSIG1−VRST0) is read out as avideo signal.

Thus, by transferring, at time point t1, the charge generated in thephotodiode 101 to the floating diffusion region 103 in all the pixelsalmost at the same time, the photodiodes in all the pixels start andstop accumulating charge at the same time, thus allowing a globalshutter operation.

FIG. 7 is a timing chart indicating an example of timing for driving thesolid-state imaging device.

The respective control signals except the control signal TRAN are thesame as those in FIG. 6. The difference is that at time points t2 and t3in addition to the time point t1, the control signal IRAN is changed tohigh level with a pulse shape. With this, three types of accumulationtime T1, T2, and T3 are provided for accumulating charge in thephotodiode 101 in each pixel. The lengths of accumulation time T1, T2,and T3 are different from each other, and when, for example, assumingthe accumulation time T1 as 30 msec as a reference, the accumulationtime T2 as 300 μsec, and the accumulation time T3 as 3 μsec, theaccumulation time T2 having a hundredth ( 1/100) length of the referenceaccumulation time T1 and the accumulation time T3 having aten-thousandth ( 1/10000) length of the reference are provided.

Since the output (amount of charge to be generated) from the photodiode101 is proportional to a production of multiplication of incident lightintensity and accumulation time, the intensity of the incident lightthat allows an output to be responsive without saturation is increasedby 100 times when the accumulation time is 1/100, and is increased by10000 times when the accumulation time is 1/10000.

As a result, each of (i) an amount of signal charge that has responded,at time point t1, to the incident light having an intensity up to thereference intensity, (ii) an amount of signal charge that has responded,at time point t2, to the incident light having an intensity up to 100times higher than the reference, and (iii) an amount of signal chargethat has responded, at time point t3, to the incident light having anintensity up to 10000 times higher than the reference, is transferred tothe floating diffusion region 103 and added therein, so that at timepoint t3, the floating diffusion region 103 holds an amount of chargethat has responded to the incident light having an intensity up to 10000times larger than the reference.

This means that the dynamic range of the pixel circuit is expanded by 80dB (20*log(10000)). Accordingly, when setting a reference dynamic rangeto a general range of 60 dB, a dynamic range of 140 dB can be obtained.

As shown in FIG. 7, an operation at the time point t4 and after is thesame as the operation shown in FIG. 6, which allows the global shutteroperation and further allows obtaining a video signal having expandeddynamic range. In the example in FIG. 7, three types of accumulationtime have been used for description, but the ratio between eachaccumulation time and the number of the types are not limited to thisexample.

According to the solid-state imaging device configured as above, it ispossible to produce advantageous effects as below.

For a first advantageous effect, when assuming different lengths ofaccumulation time as T1, T2, and T3, by setting the accumulation time T1to 30 msec as the reference, the accumulation time T2 to 300 μsec, andthe accumulation time T3 to 3 μsec, the output during the accumulationtime of 300 μsec that is a hundredth ( 1/100) of the referenceaccumulation time T1 and the output during the accumulation time of 3μsec that is a ten-thousandth ( 1/10000) of the reference are added tothe accumulation time T1, thus allowing achieving dynamic range 10000times larger than the reference. Note that in this example, three typesof accumulation time have been used for the description, but theapplication is not limited to these three types; it is possible toproduce the same advantageous effect using a combination of a normalaccumulation time and a shorter accumulation time.

A second advantageous effect allows obtaining a higher voltage at pointB than in the case of a general noise canceling circuit including twocapacitors, that is, capacitors 111 and 122 as shown in FIG. 8. Thisadvantageous effect can be produced by including, as shown in FIG. 3,the capacitor 111 and the capacitors 117, 118, 119, and 120 in the noisecanceling circuit.

As a specific example, assuming the capacitance of the capacitor 111 as3 pF and the capacitance of the capacitor 122 as 2 pF, the voltageobtained at point B is 0.6 times (3 pF/(3 pF+2 pF)) as high as thevoltage obtained from the vertical common signal line 108. In contrast,according to an implementation of the present invention, it is possibleto obtain, at point B, a voltage that is 0.86 times (3 pF/(3 pF+0.5 pF))as high as the voltage obtained from the vertical common signal line108, by dividing the capacitor 122 into the four capacitors 111, 118,119, and 120, and setting the capacitance of each of the capacitors 117,118, 119, and 120 to 0.5 pF that is a quarter (¼) of the capacitance 2pF of the capacitor 122, thus allowing increasing an output voltage by43% compared to the general case of not dividing the capacitor.

A third advantageous effect is noise reduction. Since the capacitors117, 118, 119, and 120 are connected in parallel at time point t11 afterthe voltage VRST1 is set for the capacitors 117, 118, 119, and 120, itis possible to reduce ktc noise to ½ (1/√4).

[Embodiment 2]

Subsequently, a solid-state imaging device according to a secondembodiment of the present invention will be described.

FIG. 9 is a circuit diagram showing a pixel circuit of the solid-stateimaging device according to the second embodiment of the presentinvention.

Compared to the pixel circuit 121 in the solid-state imaging deviceaccording to the first embodiment shown in FIG. 3, the pixel circuitshown in FIG. 9 includes, additionally, a MOS transistor 205 and acontrol signal RST1, with an explicit illustration of a floatingdiffusion region 209 in the partial circuit A in FIG. 3.

The MOS transistor 205 is an example of a second reset unit, and is areset transistor which sets the voltage of the floating diffusion region103 to an initializing voltage VRST1.

Note that in FIG. 9, a control signal RST2 and a voltage VRST2 are thesame as the control signal RST and the voltage VRST in FIG. 3,respectively. In addition, FIG. 9 explicitly shows a signal line thattransmits each control signal, but the illustration of each power linesupplying a corresponding one of the voltages VRST1, VRST2, and VDD isomitted.

FIG. 10 is a cross-sectional schematic diagram of a main part of thepixel circuit according to the second embodiment.

In FIG. 10, the n⁺-type impurity region 156 functions as the floatingdiffusion region 209. In addition, the MOS transistor 104 functions as acharge transfer gate (that is, a single-stage charge transfer element)through which the charge accumulated in the floating diffusion region103 is transferred to the floating diffusion region 209.

By applying voltage to the gate of the MOS transistor 104, all thecharges accumulated in the floating diffusion region 103 are transferredto the floating diffusion region 209 and accumulated therein. A voltagegenerated by the accumulated charge in the floating diffusion region 209is applied to the gate of the MOS transistor 106 via a contact not shownin the figure.

The MOS transistors 106 and 107 apply, to the vertical common signalline 108, a voltage according to the voltage of the floating diffusionregion 209.

Here, the voltage VRST1 applied to the floating diffusion region 103 maybe lower than the voltage VRST2 applied to the is floating diffusionregion 209. This allows a complete transfer of the charge from thefloating diffusion region 103 to the floating diffusion region 209.

The impurity concentration of each of the impurity regions shown in FIG.10 is the same as the impurity concentration described in FIG. 5.

As described earlier, in order to suppress leakage current, it ispreferable that the n-type impurity region 154 as the floating diffusionregion 103 be formed at low concentration.

In contrast, a contact connected to the gate of the MOS transistor 106is provided in the n⁺-type impurity region 156 as the floating diffusionregion 209; accordingly, it is possible, by increasing the n⁺-typeimpurity concentration, to prevent a depletion region from spreading tothe surface of the substrate 151 even when voltage is applied, thusreducing leakage current. In addition, by forming the n⁺-type impurityregion 156 at high concentration, it is possible to increase thecapacitance of the floating diffusion region 209 and to thereby increasethe amount of charge accumulation.

FIG. 11 is a schematic diagram showing a basic layout of the pixelcircuits according to the second embodiment as viewed from top of thesubstrate.

In this pixel circuit, from top left to bottom, the photodiode 101, theMOS transistor 102, the floating diffusion region 103, the MOStransistor 104, and the floating diffusion region 209 are arrangedadjacent to each other in this order. In addition, the MOS transistor205 is placed adjacent to the floating diffusion region 103 on the rightin the figure, and the MOS transistor 105 is placed adjacent to thefloating diffusion region 209 on the right in the figure. In addition,the MOS transistors 106 and 107 are placed to the right of thephotodiode 101 in the figure. In addition to these, as signal lines andpower lines, seven to nine lines are placed although not shown in thefigure.

According to the layout as above, the n-type impurity region 154 isshared between the drain of the MOS transistor 102 and the floatingdiffusion region 103, and the n⁺-type impurity region 156 is sharedbetween the drain of the MOS transistor 104 and the floating diffusionregion 209, thus substantially reducing area to be occupied by thecapacitor when viewed from top of the substrate. As a result, thephotodiode 101 can secure a high aperture ratio that is a ratio of areaoccupied by the photodiode 101 in an area of one pixel.

When it is important to increase the aperture ratio, the voltages VRST1and VRST2 described earlier may be supplied as the same voltage using asingle power line. Furthermore, the voltages VRST1, VRST2, and VDD maybe supplied as the same voltage using the single power line.

As an example, when assuming a cell size of one pixel as 5.6 μm×5.6 μmand using a 0.25-μm CMOS rule, a line covers approximately 5% of thearea of the cell of one pixel; when assuming, for example, a referenceaperture ratio in the case of not sharing the power line as 30%, theaperture ratio is increased to 35% by reducing one of the power lines,and can further be increased to 40% by reducing another one of the powerlines.

In addition, since the pixel circuit accumulates signal charge using thefloating diffusion regions 103 and 209, it is possible to realize apixel circuit which allows expanding dynamic range, using a simpleconfiguration which, for example, does not include a MOS-type capacitorfor accumulating signal charge.

Note that the p-type impurity regions 153 and 155 in the surface of thesubstrate 151 in the floating diffusion regions 103 and 209 areprovided, as described earlier, to suppress leakage current in and outof the floating diffusion regions 103 and 209; thus, p-type impurityregions 153 and 155 can be omitted from the configuration intended toexpand dynamic range of the pixel circuit.

An imaging device includes a plurality of such pixel circuits arrangedin an array.

An operation of the solid-state imaging device configured as above willbe described.

FIG. 12 is a timing chart showing an example of timing for driving thepixel circuit of the solid-state imaging device according to the secondembodiment.

A basic concept of driving timing as shown in FIG. 12 is the same as thedriving timing shown in FIG. 7 in that: all the amounts of chargeaccumulated in the photodiode 101 during three types of accumulationtime having different lengths are transferred to the floating diffusionregion 103 and added therein, so as to expand dynamic range.

The following will omit the description of the points common to thedriving timing in FIG. 7, and will only describe the difference. Notethat the control signal RST2 corresponds to the control signal RST inFIG. 7 as described earlier.

First, during the charge accumulation period, an operation oftransferring, to the floating diffusion region 103, the chargeaccumulated in the photodiode 101 through photoelectric conversion willbe performed.

At time point t0, by changing the control signal RST1 to high level witha pulse shape, the charge accumulated in the floating diffusion region103 is discharged to a supply of the voltage VRST1 via the MOStransistor 205.

At time points t1, t2, and t3, as in FIG. 7, by changing the controlsignal TRAN to high level with a pulse shape, each amount of chargeaccumulated in the photodiode 101 during different types of accumulationtime T1, T2, and T3 is transferred to the floating diffusion region 103and added therein. As described in the first embodiment, this expandsthe dynamic range.

Subsequently, during the charge reading period, an operation oftransmitting a signal to the vertical common signal line 108 isperformed.

With the control signal SEL held at high level, the control signal RST2is changed to high level with a pulse shape at time point t4. With this,a voltage according to the voltage VRST2 is set for the floatingdiffusion region 209 via the MOS transistor 105.

The MOS transistors 106 and 107 apply, to the vertical common signalline 108, a voltage according to the voltage set for the floatingdiffusion region 209, and a noise canceling unit not shown in the figureholds the voltage obtained from the vertical common signal line 108 asnoise voltage that is to be subsequently offset by the signal voltage.For the noise canceling unit, for example, a general circuit as shown inFIG. 8 may be used, or the circuit shown in FIG. 3 may also be used.

At time point t5, the control signal READ is changed to high level witha pulse shape. This causes the electric charge accumulated in thefloating diffusion region 103 to be transferred to the floatingdiffusion region 209 via the MOS transistor 104. The voltage of thefloating diffusion region 209 changes according to the amount of thetransferred charge (that is, an amplitude of the signal component).

The MOS transistors 106 and 107 apply, to the vertical common signalline 108, a voltage according to the changed voltage of the floatingdiffusion region 209, and the noise canceling unit holds the voltageobtained from the vertical common signal line 108 as a voltage includinga noise component and a signal component.

The noise canceling unit detects a difference between a previously-heldvoltage and a subsequently-held voltage as a signal component.

In the case of using the general circuit in FIG. 8 for the noisecanceling unit, the signal component is detected as an amount of changefrom the voltage VCLDC at point B. In addition, the method of detectingthe signal component in the case of using the circuit shown in FIG. 3for the noise canceling unit has been described in the first embodiment.

Such a noise canceling operation also removes variation in the thresholdof the MOS transistor 106 in each pixel, thus making it possible toobtain a highly-sensitive and high-quality image.

According to the solid-state imaging device configured as above, it ispossible to produce an advantageous effect as below.

By concurrently performing the operation during the charge accumulationon a plurality of pixels arranged in an array in the solid-state imagingdevice, the photodiodes in all the pixels start and stop accumulatingcharge at the same time, thus allowing a global shutter operation. Theoperation during the charge reading period is sequentially performed perrow, for example, on each pixel in each row in the array during ahorizontal blanking period for the row.

In addition, all the amounts of charge accumulated in the photodiode 101during the three different types of accumulation time are completelytransferred to the floating diffusion region 103 and added therein, thusmaking it possible to expand the dynamic range of the pixel circuit.

[Industrial Applicability]

An imaging element according to an implementation of the presentinvention is widely applicable to a digital camera, a mobile informationterminal device, an in-vehicle camera, a monitoring camera, and so on.

[Reference Signs List]

101 Photodiode

102, 104, 105, 106, 107, 110, 112, 113, 114, 115, 116, 205 MOStransistor

103, 209 Floating diffusion region

108 Vertical common signal line

109 Amplifier

111, 117, 118, 119, 120, 122 Capacitor

121 Pixel circuit

151 Substrate

152 n⁻-type impurity region

153, 155 p-type impurity region

154 n-type impurity region

156, 171 n⁺-type impurity region

163, 168, 170 Gate electrode

371 PD unit

372 Transfer transistor

373 FD region

374 First capacitor

375 Second capacitor

376 Reset transistor

377 First accumulation transistor

378 Second accumulation transistor

379 Amplifying transistor

380 Selection transistor

The invention claimed is:
 1. A solid-state imaging device including aplurality of pixel circuits two-dimensionally arranged on asemiconductor substrate, said solid-state imaging device comprising: aphotoelectric conversion unit configured to generate a charge fromincident light; a first transfer unit connected to said photoelectricconversion unit and configured to transfer the charge; a firstaccumulation unit configured to accumulate the charge via said firsttransfer unit; a second transfer unit connected to said firstaccumulation unit and connected in series to said first transfer unit;an output unit configured to output a signal voltage that is a voltageaccording to an amount of the charge via said second transfer unit; anda reset unit configured to set a voltage of a connection point betweensaid second transfer unit and said output unit to a reset voltage,wherein said output unit is configured to output a reference voltage ina state where the reset voltage is applied to the connection point, saidphotoelectric conversion unit generates a first charge while theincident light enters said photoelectric conversion unit during a firstaccumulation time within a first frame period, said photoelectricconversion unit generates a second charge while the incident lightenters said photoelectric conversion unit during a second accumulationtime within the first frame period, the first accumulation time isdifferent from the second accumulation time, the first transfer unit isconfigured to transfer the first charge and the second charge to thefirst accumulation unit, said first accumulation unit is configured toadd and accumulate the first charge and the second charge, and only onepicture is generated during the first frame period based on the firstcharge and the second charge accumulated by the first accumulation unit.2. The solid-state imaging device according to claim 1, furthercomprising a differential circuit which detects a difference between thesignal voltage and the reference voltage, wherein said differentialcircuit includes: a first capacitor and a second capacitor that areconnected in series; and an initializing switch through which aninitializing voltage that is predetermined is applied to a connectionpoint between said first and second capacitors, and in a state where theinitializing voltage is applied to the connection point, saiddifferential circuit holds a difference voltage in said first capacitorand the initializing voltage in said second capacitor, and subsequentlydivides the reference voltage between said first and second capacitors,the difference voltage being a difference between the signal voltage andthe initializing voltage.
 3. The solid-state imaging device according toclaim 1, wherein each of said first and second transfer units includes aMOS transistor, and a drain of said first transfer unit is connected toa source of said second transfer unit.
 4. The solid-state imaging deviceaccording to claim 1, wherein said photoelectric conversion unit, saidfirst transfer unit, said first accumulation unit, said second transferunit, said output unit, and said reset unit are provided in each of saidplurality of pixel circuits.
 5. The solid-state imaging device accordingto claim 1, wherein said second transfer unit includes a MOS transistor.6. The solid-state imaging device according to claim 1, wherein saidfirst accumulation unit has no contact with a metal material.
 7. Thesolid-state imaging device according to claim 1, wherein the firstaccumulation unit includes a first region of a first conductivity typeand a second region having a second conductivity type different from thefirst conductivity type, and the second region is disposed on the firstregion.
 8. The solid-state imaging device according to claim 2, whereinsaid second capacitor includes a plurality of separate capacitors one ofwhich can be selectively connected in series to said first capacitor,and all of which can be coupled in parallel, and said differentialcircuit divides the reference voltage between said first capacitor andeach of said plurality of separate capacitors, and subsequently couplesall of said plurality of separate capacitors in parallel.
 9. Thesolid-state imaging device according to claim 7, wherein thephotoelectric conversion unit includes a third region of the firstconductivity type and a fourth region of the second conductivity type,the fourth region is disposed on the third region, and an impurityconcentration of the first conductivity type in the first region ishigher than an impurity concentration of the first conductivity type inthe third region.